diff options
| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2025-04-03 11:19:25 +0200 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2025-04-29 11:05:34 +0200 |
| commit | 51b252cce172cbfb21dfd5e544dcbefc649f3daa (patch) | |
| tree | 6917cc0ea62a8ff9d3b899d38f8cfb362e67d82a /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | ac3a4b17e03b079c00eb61456364bcdbf65f3436 (diff) | |
mtd: spinand: Define octal operations
SPI NAND chips may support octal "read from cache" and "program load"
transfers. List the opcodes by defining the relevant macros describing
these operations.
However, due to the hardware available I had, 0x82 and 0xc2 are
untested and given as reference, only 0xc4 could be (successfully)
tested.
Controllers supporting operations mixing SDR and DTR operations might
even leverage octal DTR data I/O transfers.
Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions