diff options
| author | Ben Widawsky <ben.widawsky@intel.com> | 2022-01-23 16:29:05 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-08 22:57:27 -0800 |
| commit | 8baa787b93dbda6b24081297b934e8edd886d4bb (patch) | |
| tree | 03d3d7629f710abe9fa12138adbad6b0228df325 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 46c6ad27625ca00f59903585e41667d7a45b4eb8 (diff) | |
cxl/pci: Add new DVSEC definitions
In preparation for properly supporting memory active timeout, and later
on, other attributes obtained from DVSEC fields, add the full list of
DVSEC identifiers from the CXL 2.0 specification.
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huwei.com> (v1)
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Link: https://lore.kernel.org/r/164298414567.3018233.12005290051592771878.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions