diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-06-08 23:30:49 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-06-13 19:04:25 +0300 |
| commit | a43d92812077b15c8e3bfdf80dc9d8596b503c60 (patch) | |
| tree | cb4c8decf5d94797efcb5497de6bc6554c537f8d /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | d4121327ac6af65327c1ae90bac89e1575f0f277 (diff) | |
drm/i915/dsi: Gate DSI clocks earlier
The clock gating step is in the wrong spot compared to the
TGL+ bspec sequence. Move it the right place. Windows also
seems to use the TGL+ order here always.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230608203057.23759-6-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions