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author | Biju Das <biju.das.jz@bp.renesas.com> | 2023-08-25 10:05:18 +0100 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-05 14:25:00 +0200 |
commit | feab6a13ae63101e62a9f3b0e552f13067218e6f (patch) | |
tree | ca1f1751cffe1c90c19e80847239724ddf538f87 /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | 75b696a43fdd1740359cf967a6cbc9ae06fb616d (diff) |
arm64: dts: renesas: rz-smarc: Use versa3 clk for audio mclk
Currently audio mclk uses a fixed clk of 11.2896MHz (multiple of 44.1kHz).
Replace this fixed clk with the programmable versa3 clk that can provide
the clocking to support both 44.1kHz (with a clock of 11.2896MHz) and
48kHz (with a clock of 12.2880MHz), based on audio sampling rate for
playback and record.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230825090518.87394-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions