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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-09-06 16:53:23 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2025-09-11 18:03:10 +0200 |
| commit | fc02f529a8dbf617f6d211cb693f56a842b6dbe5 (patch) | |
| tree | aa1f53c7a9d45f1d2f25031f9f1341a1986b09bc /tools/perf/scripts/python/sched-migration.py | |
| parent | 6b670e53ac6ecd531d90324e9ef87a029d2c98b9 (diff) | |
dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
Tegra30 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers.
Add ids for these clocks. Additionally, move TEGRA30_CLK_CLK_MAX into
clk-tegra30 source.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions