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| author | Nishanth Menon <nm@ti.com> | 2021-11-12 22:36:38 -0600 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2021-12-03 17:19:04 +0530 |
| commit | d0c826106f3fc11ff97285102b576b65576654ae (patch) | |
| tree | f39d93560c3df0f4118a51e7d429aa7b253e68a6 /tools/perf/scripts/python/stackcollapse.py | |
| parent | a27a93bf70045be54b594fa8482959ffb84166d7 (diff) | |
arm64: dts: ti: k3-j7200: Fix the L2 cache sets
A72's L2 cache[1] on J7200[2] is 1MB. A72's L2 is fixed line length of
64 bytes and 16-way set-associative cache structure.
1MB of L2 / 64 (line length) = 16384 ways
16384 ways / 16 = 1024 sets
Fix the l2 cache-sets.
[1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
[2] https://www.ti.com/lit/pdf/spruiu1
Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211113043638.4358-1-nm@ti.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions