diff options
15 files changed, 1433 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml new file mode 100644 index 000000000000..3b8b85be5cd0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-ispcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: ISP Top core + - description: ISP Top Axi + - description: NOC ISP Bus + - description: external DVP + + clock-names: + items: + - const: isp_top_core + - const: isp_top_axi + - const: noc_bus_isp_axi + - const: dvp_clk + + resets: + items: + - description: ISP Top core + - description: ISP Top Axi + - description: NOC ISP Bus + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + + power-domains: + maxItems: 1 + description: + ISP domain power + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - '#clock-cells' + - '#reset-cells' + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + #include <dt-bindings/power/starfive,jh7110-pmu.h> + #include <dt-bindings/reset/starfive,jh7110-crg.h> + + ispcrg: clock-controller@19810000 { + compatible = "starfive,jh7110-ispcrg"; + reg = <0x19810000 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, + <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, + <&dvp_clk>; + clock-names = "isp_top_core", "isp_top_axi", + "noc_bus_isp_axi", "dvp_clk"; + resets = <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, + <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_ISP>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml new file mode 100644 index 000000000000..be8300ce86d0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PLL Clock Generator + +description: + These PLLs are high speed, low jitter frequency synthesizers in the JH7110. + Each PLL works in integer mode or fraction mode, with configuration + registers in the sys syscon. So the PLLs node should be a child of + SYS-SYSCON node. + The formula for calculating frequency is + Fvco = Fref * (NI + NF) / M / Q1 + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-pll + + clocks: + maxItems: 1 + description: Main Oscillator (24 MHz) + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml new file mode 100644 index 000000000000..b64ccd84200a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 System-Top-Group Clock and Reset Generator + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-stgcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: HIFI4 core + - description: STG AXI/AHB + - description: USB (125 MHz) + - description: CPU Bus + - description: HIFI4 Axi + - description: NOC STG Bus + - description: APB Bus + + clock-names: + items: + - const: osc + - const: hifi4_core + - const: stg_axiahb + - const: usb_125m + - const: cpu_bus + - const: hifi4_axi + - const: nocstg_bus + - const: apb_bus + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + + stgcrg: clock-controller@10230000 { + compatible = "starfive,jh7110-stgcrg"; + reg = <0x10230000 0x10000>; + clocks = <&osc>, + <&syscrg JH7110_SYSCLK_HIFI4_CORE>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_USB_125M>, + <&syscrg JH7110_SYSCLK_CPU_BUS>, + <&syscrg JH7110_SYSCLK_HIFI4_AXI>, + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, + <&syscrg JH7110_SYSCLK_APB_BUS>; + clock-names = "osc", "hifi4_core", + "stg_axiahb", "usb_125m", + "cpu_bus", "hifi4_axi", + "nocstg_bus", "apb_bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml index 84373ae31644..5ba0a885aa80 100644 --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml @@ -27,6 +27,9 @@ properties: - description: External I2S RX left/right channel clock - description: External TDM clock - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 - items: - description: Main Oscillator (24 MHz) @@ -38,6 +41,9 @@ properties: - description: External I2S RX left/right channel clock - description: External TDM clock - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 clock-names: oneOf: @@ -52,6 +58,9 @@ properties: - const: i2srx_lrck_ext - const: tdm_ext - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out - items: - const: osc @@ -63,6 +72,9 @@ properties: - const: i2srx_lrck_ext - const: tdm_ext - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out '#clock-cells': const: 1 @@ -93,12 +105,14 @@ examples: <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>; + <&tdm_ext>, <&mclk_ext>, + <&pllclk 0>, <&pllclk 1>, <&pllclk 2>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext"; + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml new file mode 100644 index 000000000000..af77bd8c86b1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Video-Output Clock and Reset Generator + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-voutcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Vout Top core + - description: Vout Top Ahb + - description: Vout Top Axi + - description: Vout Top HDMI MCLK + - description: I2STX0 BCLK + - description: external HDMI pixel + + clock-names: + items: + - const: vout_src + - const: vout_top_ahb + - const: vout_top_axi + - const: vout_top_hdmitx0_mclk + - const: i2stx0_bclk + - const: hdmitx0_pixelclk + + resets: + maxItems: 1 + description: Vout Top core + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + + power-domains: + maxItems: 1 + description: + Vout domain power + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - '#clock-cells' + - '#reset-cells' + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + #include <dt-bindings/power/starfive,jh7110-pmu.h> + #include <dt-bindings/reset/starfive,jh7110-crg.h> + + voutcrg: clock-controller@295C0000 { + compatible = "starfive,jh7110-voutcrg"; + reg = <0x295C0000 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmitx0_pixelclk>; + clock-names = "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_VOUT>; + }; diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml new file mode 100644 index 000000000000..0039319e91fe --- /dev/null +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 SoC system controller + +maintainers: + - William Qiu <william.qiu@starfivetech.com> + +description: + The StarFive JH7110 SoC system controller provides register information such + as offset, mask and shift to configure related modules such as MMC and PCIe. + +properties: + compatible: + oneOf: + - items: + - const: starfive,jh7110-sys-syscon + - const: syscon + - const: simple-mfd + - items: + - enum: + - starfive,jh7110-aon-syscon + - starfive,jh7110-stg-syscon + - const: syscon + + reg: + maxItems: 1 + + clock-controller: + $ref: /schemas/clock/starfive,jh7110-pll.yaml# + type: object + + "#power-domain-cells": + const: 1 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: starfive,jh7110-sys-syscon + then: + required: + - clock-controller + else: + properties: + clock-controller: false + - if: + properties: + compatible: + contains: + const: starfive,jh7110-aon-syscon + then: + required: + - "#power-domain-cells" + else: + properties: + "#power-domain-cells": false + +additionalProperties: false + +examples: + - | + syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x10240000 0x1000>; + }; + + syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x13030000 0x1000>; + + clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; + }; + + syscon@17010000 { + compatible = "starfive,jh7110-aon-syscon", "syscon"; + reg = <0x17010000 0x1000>; + #power-domain-cells = <1>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index aee340630eca..44b4358c3c3a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20282,6 +20282,12 @@ S: Supported F: Documentation/devicetree/bindings/mmc/starfive* F: drivers/mmc/host/dw_mmc-starfive.c +STARFIVE JH7110 SYSCON +M: William Qiu <william.qiu@starfivetech.com> +M: Xingyu Wu <xingyu.wu@starfivetech.com> +S: Supported +F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml + STARFIVE JH7110 TDM DRIVER M: Walker Chen <walker.chen@starfivetech.com> S: Maintained @@ -20331,6 +20337,7 @@ STARFIVE SOC DRIVERS M: Conor Dooley <conor@kernel.org> S: Maintained T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +F: Documentation/devicetree/bindings/soc/starfive/ F: drivers/soc/starfive/ STARFIVE TRNG DRIVER diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index 170956846d49..0141504c0f5c 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -1,4 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 +# Enables support for device-tree overlays +DTC_FLAGS_jh7100-beaglev-starlight := -@ +DTC_FLAGS_jh7100-starfive-visionfive-v1 := -@ +DTC_FLAGS_jh7110-starfive-visionfive-2-v1.2a := -@ +DTC_FLAGS_jh7110-starfive-visionfive-2-v1.3b := -@ + dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 4218621ea3b9..35ab54fb235f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -80,6 +80,31 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <15000>; + + thermal-sensors = <&sfctemp>; + + trips { + cpu_alert0 { + /* milliCelsius */ + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit { + /* milliCelsius */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + osc_sys: osc_sys { compatible = "fixed-clock"; #clock-cells = <0>; @@ -248,5 +273,17 @@ resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, <&rstgen JH7100_RSTN_WDT>; }; + + sfctemp: temperature-sensor@124a0000 { + compatible = "starfive,jh7100-temp"; + reg = <0x0 0x124a0000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_TEMP_SENSE>, + <&clkgen JH7100_CLK_TEMP_APB>; + clock-names = "sense", "bus"; + resets = <&rstgen JH7100_RSTN_TEMP_SENSE>, + <&rstgen JH7100_RSTN_TEMP_APB>; + reset-names = "sense", "bus"; + #thermal-sensor-cells = <0>; + }; }; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts index 4af3300f3cf3..205a13d8c8b1 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts @@ -11,3 +11,16 @@ model = "StarFive VisionFive 2 v1.2A"; compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110"; }; + +&gmac1 { + phy-mode = "rmii"; + assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>, + <&syscrg JH7110_SYSCLK_GMAC1_RX>; + assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>, + <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; +}; + +&phy0 { + rx-internal-delay-ps = <1900>; + tx-internal-delay-ps = <1350>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts index 9230cc3d8946..d4ea4a2c0b9b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts @@ -11,3 +11,34 @@ model = "StarFive VisionFive 2 v1.3B"; compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; }; + +&gmac0 { + starfive,tx-use-rgmii-clk; + assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; + assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; +}; + +&gmac1 { + starfive,tx-use-rgmii-clk; + assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; + assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; +}; + +&phy0 { + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,tx-clk-1000-inverted; + motorcomm,rx-clk-drv-microamp = <3970>; + motorcomm,rx-data-drv-microamp = <2910>; + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; +}; + +&phy1 { + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,rx-clk-drv-microamp = <3970>; + motorcomm,rx-data-drv-microamp = <2910>; + rx-internal-delay-ps = <300>; + tx-internal-delay-ps = <0>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index fa0061eb33a7..d79f94432b27 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -11,10 +11,14 @@ / { aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; i2c0 = &i2c0; i2c2 = &i2c2; i2c5 = &i2c5; i2c6 = &i2c6; + mmc0 = &mmc0; + mmc1 = &mmc1; serial0 = &uart0; }; @@ -38,6 +42,10 @@ }; }; +&dvp_clk { + clock-frequency = <74250000>; +}; + &gmac0_rgmii_rxin { clock-frequency = <125000000>; }; @@ -54,6 +62,10 @@ clock-frequency = <50000000>; }; +&hdmitx0_pixelclk { + clock-frequency = <297000000>; +}; + &i2srx_bclk_ext { clock-frequency = <12288000>; }; @@ -86,6 +98,38 @@ clock-frequency = <49152000>; }; +&gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy1: ethernet-phy@1 { + reg = <0>; + }; + }; +}; + &i2c0 { clock-frequency = <100000>; i2c-sda-hold-time-ns = <300>; @@ -123,12 +167,28 @@ #interrupt-cells = <1>; regulators { + vcc_3v3: dcdc1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3"; + }; + vdd_cpu: dcdc2 { regulator-always-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1540000>; regulator-name = "vdd-cpu"; }; + + emmc_vdd: aldo4 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "emmc_vdd"; + }; }; }; }; @@ -143,6 +203,83 @@ status = "okay"; }; +&mmc0 { + max-frequency = <100000000>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + cap-mmc-hw-reset; + post-power-on-delay-ms = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_vdd>; + status = "okay"; +}; + +&mmc1 { + max-frequency = <100000000>; + bus-width = <4>; + no-sdio; + no-mmc; + broken-cd; + cap-sd-highspeed; + post-power-on-delay-ms = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "okay"; +}; + +&qspi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nor_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + cdns,read-delay = <5>; + spi-max-frequency = <12000000>; + cdns,tshsl-ns = <1>; + cdns,tsd2d-ns = <1>; + cdns,tchsh-ns = <1>; + cdns,tslch-ns = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + spl@0 { + reg = <0x0 0x80000>; + }; + uboot-env@f0000 { + reg = <0xf0000 0x10000>; + }; + uboot@100000 { + reg = <0x100000 0x400000>; + }; + reserved-data@600000 { + reg = <0x600000 0x1000000>; + }; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + spi_dev0: spi@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + &sysgpio { i2c0_pins: i2c0-0 { i2c-pins { @@ -200,6 +337,109 @@ }; }; + mmc0_pins: mmc0-0 { + rst-pins { + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, + GPOEN_ENABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mmc-pins { + pinmux = <PINMUX(64, 0)>, + <PINMUX(65, 0)>, + <PINMUX(66, 0)>, + <PINMUX(67, 0)>, + <PINMUX(68, 0)>, + <PINMUX(69, 0)>, + <PINMUX(70, 0)>, + <PINMUX(71, 0)>, + <PINMUX(72, 0)>, + <PINMUX(73, 0)>; + bias-pull-up; + drive-strength = <12>; + input-enable; + }; + }; + + mmc1_pins: mmc1-0 { + clk-pins { + pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK, + GPOEN_ENABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mmc-pins { + pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD, + GPOEN_SYS_SDIO1_CMD, + GPI_SYS_SDIO1_CMD)>, + <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0, + GPOEN_SYS_SDIO1_DATA0, + GPI_SYS_SDIO1_DATA0)>, + <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1, + GPOEN_SYS_SDIO1_DATA1, + GPI_SYS_SDIO1_DATA1)>, + <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2, + GPOEN_SYS_SDIO1_DATA2, + GPI_SYS_SDIO1_DATA2)>, + <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3, + GPOEN_SYS_SDIO1_DATA3, + GPI_SYS_SDIO1_DATA3)>; + bias-pull-up; + drive-strength = <12>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + + spi0_pins: spi0-0 { + mosi-pins { + pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD, + GPOEN_ENABLE, + GPI_NONE)>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + miso-pins { + pinmux = <GPIOMUX(53, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_SPI0_RXD)>; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + + sck-pins { + pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK, + GPOEN_ENABLE, + GPI_SYS_SPI0_CLK)>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + ss-pins { + pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS, + GPOEN_ENABLE, + GPI_SYS_SPI0_FSS)>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + }; + uart0_pins: uart0-0 { tx-pins { pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, @@ -223,6 +463,46 @@ slew-rate = <0>; }; }; + + tdm_pins: tdm-0 { + tx-pins { + pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD, + GPOEN_ENABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pinmux = <GPIOMUX(61, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_RXD)>; + input-enable; + }; + + sync-pins { + pinmux = <GPIOMUX(63, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_SYNC)>; + input-enable; + }; + + pcmclk-pins { + pinmux = <GPIOMUX(38, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_CLK)>; + input-enable; + }; + }; +}; + +&tdm { + pinctrl-names = "default"; + pinctrl-0 = <&tdm_pins>; + status = "okay"; }; &uart0 { @@ -231,6 +511,10 @@ status = "okay"; }; +&usb0 { + dr_mode = "peripheral"; +}; + &U74_1 { cpu-supply = <&vdd_cpu>; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index ec2e70011a73..9aa563898868 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -6,7 +6,9 @@ /dts-v1/; #include <dt-bindings/clock/starfive,jh7110-crg.h> +#include <dt-bindings/power/starfive,jh7110-pmu.h> #include <dt-bindings/reset/starfive,jh7110-crg.h> +#include <dt-bindings/thermal/thermal.h> / { compatible = "starfive,jh7110"; @@ -56,6 +58,7 @@ operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; clock-names = "cpu"; + #cooling-cells = <2>; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -85,6 +88,7 @@ operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; clock-names = "cpu"; + #cooling-cells = <2>; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -114,6 +118,7 @@ operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; clock-names = "cpu"; + #cooling-cells = <2>; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -143,6 +148,7 @@ operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; clock-names = "cpu"; + #cooling-cells = <2>; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -197,6 +203,47 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <15000>; + + thermal-sensors = <&sfctemp>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit { + /* milliCelsius */ + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + dvp_clk: dvp-clock { + compatible = "fixed-clock"; + clock-output-names = "dvp_clk"; + #clock-cells = <0>; + }; gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; clock-output-names = "gmac0_rgmii_rxin"; @@ -221,6 +268,12 @@ #clock-cells = <0>; }; + hdmitx0_pixelclk: hdmitx0-pixel-clock { + compatible = "fixed-clock"; + clock-output-names = "hdmitx0_pixelclk"; + #clock-cells = <0>; + }; + i2srx_bclk_ext: i2srx-bclk-ext-clock { compatible = "fixed-clock"; clock-output-names = "i2srx_bclk_ext"; @@ -263,6 +316,13 @@ #clock-cells = <0>; }; + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <15>; + snps,rd_osr_lmt = <15>; + snps,blen = <256 128 64 32 0 0 0>; + }; + tdm_ext: tdm-ext-clock { compatible = "fixed-clock"; clock-output-names = "tdm_ext"; @@ -386,6 +446,149 @@ status = "disabled"; }; + spi0: spi@10060000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10060000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>, + <&syscrg JH7110_SYSCLK_SPI0_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI0_APB>; + interrupts = <38>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@10070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>, + <&syscrg JH7110_SYSCLK_SPI1_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI1_APB>; + interrupts = <39>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@10080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10080000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>, + <&syscrg JH7110_SYSCLK_SPI2_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI2_APB>; + interrupts = <40>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + tdm: tdm@10090000 { + compatible = "starfive,jh7110-tdm"; + reg = <0x0 0x10090000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>, + <&syscrg JH7110_SYSCLK_TDM_APB>, + <&syscrg JH7110_SYSCLK_TDM_INTERNAL>, + <&syscrg JH7110_SYSCLK_TDM_TDM>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&tdm_ext>; + clock-names = "tdm_ahb", "tdm_apb", + "tdm_internal", "tdm", + "mclk_inner", "tdm_ext"; + resets = <&syscrg JH7110_SYSRST_TDM_AHB>, + <&syscrg JH7110_SYSRST_TDM_APB>, + <&syscrg JH7110_SYSRST_TDM_CORE>; + dmas = <&dma 20>, <&dma 21>; + dma-names = "rx","tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + usb0: usb@10100000 { + compatible = "starfive,jh7110-usb"; + ranges = <0x0 0x0 0x10100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + starfive,stg-syscon = <&stg_syscon 0x4>; + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, + <&stgcrg JH7110_STGCLK_USB0_STB>, + <&stgcrg JH7110_STGCLK_USB0_APB>, + <&stgcrg JH7110_STGCLK_USB0_AXI>, + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; + resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, + <&stgcrg JH7110_STGRST_USB0_APB>, + <&stgcrg JH7110_STGRST_USB0_AXI>, + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; + reset-names = "pwrup", "apb", "axi", "utmi_apb"; + status = "disabled"; + + usb_cdns3: usb@0 { + compatible = "cdns,usb3"; + reg = <0x0 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <100>, <108>, <110>; + interrupt-names = "host", "peripheral", "otg"; + phys = <&usbphy0>; + phy-names = "cdns3,usb2-phy"; + }; + }; + + usbphy0: phy@10200000 { + compatible = "starfive,jh7110-usb-phy"; + reg = <0x0 0x10200000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_USB_125M>, + <&stgcrg JH7110_STGCLK_USB0_APP_125>; + clock-names = "125m", "app_125m"; + #phy-cells = <0>; + }; + + pciephy0: phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10210000 0x0 0x10000>; + #phy-cells = <0>; + }; + + pciephy1: phy@10220000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10220000 0x0 0x10000>; + #phy-cells = <0>; + }; + + stgcrg: clock-controller@10230000 { + compatible = "starfive,jh7110-stgcrg"; + reg = <0x0 0x10230000 0x0 0x10000>; + clocks = <&osc>, + <&syscrg JH7110_SYSCLK_HIFI4_CORE>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_USB_125M>, + <&syscrg JH7110_SYSCLK_CPU_BUS>, + <&syscrg JH7110_SYSCLK_HIFI4_AXI>, + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, + <&syscrg JH7110_SYSCLK_APB_BUS>; + clock-names = "osc", "hifi4_core", + "stg_axiahb", "usb_125m", + "cpu_bus", "hifi4_axi", + "nocstg_bus", "apb_bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + stg_syscon: syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x0 0x10240000 0x0 0x1000>; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>; @@ -473,6 +676,97 @@ status = "disabled"; }; + qspi: spi@13010000 { + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg = <0x0 0x13010000 0x0 0x10000>, + <0x0 0x21000000 0x0 0x400000>; + interrupts = <25>; + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, + <&syscrg JH7110_SYSCLK_QSPI_AHB>, + <&syscrg JH7110_SYSCLK_QSPI_APB>; + clock-names = "ref", "ahb", "apb"; + resets = <&syscrg JH7110_SYSRST_QSPI_APB>, + <&syscrg JH7110_SYSRST_QSPI_AHB>, + <&syscrg JH7110_SYSRST_QSPI_REF>; + reset-names = "qspi", "qspi-ocp", "rstc_ref"; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + status = "disabled"; + }; + + spi3: spi@12070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>, + <&syscrg JH7110_SYSCLK_SPI3_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI3_APB>; + interrupts = <52>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@12080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12080000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>, + <&syscrg JH7110_SYSCLK_SPI4_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI4_APB>; + interrupts = <53>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@12090000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12090000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>, + <&syscrg JH7110_SYSCLK_SPI5_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI5_APB>; + interrupts = <54>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@120a0000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x120A0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>, + <&syscrg JH7110_SYSCLK_SPI6_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI6_APB>; + interrupts = <55>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sfctemp: temperature-sensor@120e0000 { + compatible = "starfive,jh7110-temp"; + reg = <0x0 0x120e0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>, + <&syscrg JH7110_SYSCLK_TEMP_APB>; + clock-names = "sense", "bus"; + resets = <&syscrg JH7110_SYSRST_TEMP_CORE>, + <&syscrg JH7110_SYSRST_TEMP_APB>; + reset-names = "sense", "bus"; + #thermal-sensor-cells = <0>; + }; + syscrg: clock-controller@13020000 { compatible = "starfive,jh7110-syscrg"; reg = <0x0 0x13020000 0x0 0x10000>; @@ -480,16 +774,31 @@ <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>; + <&tdm_ext>, <&mclk_ext>, + <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL1_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext"; + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; }; + sys_syscon: syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x0 0x13030000 0x0 0x1000>; + + pllclk: clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; + }; + sysgpio: pinctrl@13040000 { compatible = "starfive,jh7110-sys-pinctrl"; reg = <0x0 0x13040000 0x0 0x10000>; @@ -512,6 +821,155 @@ <&syscrg JH7110_SYSRST_WDT_CORE>; }; + crypto: crypto@16000000 { + compatible = "starfive,jh7110-crypto"; + reg = <0x0 0x16000000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, + <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; + clock-names = "hclk", "ahb"; + interrupts = <28>; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + dmas = <&sdma 1 2>, <&sdma 0 2>; + dma-names = "tx", "rx"; + }; + + sdma: dma-controller@16008000 { + compatible = "arm,pl080", "arm,primecell"; + arm,primecell-periphid = <0x00041080>; + reg = <0x0 0x16008000 0x0 0x4000>; + interrupts = <29>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>; + clock-names = "apb_pclk"; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + lli-bus-interface-ahb1; + mem-bus-interface-ahb1; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; + + rng: rng@1600c000 { + compatible = "starfive,jh7110-trng"; + reg = <0x0 0x1600C000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, + <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; + clock-names = "hclk", "ahb"; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + interrupts = <30>; + }; + + mmc0: mmc@16010000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; + reset-names = "reset"; + interrupts = <74>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; + status = "disabled"; + }; + + mmc1: mmc@16020000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; + reset-names = "reset"; + interrupts = <75>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; + status = "disabled"; + }; + + gmac0: ethernet@16030000 { + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg = <0x0 0x16030000 0x0 0x10000>; + clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, + <&aoncrg JH7110_AONCLK_GMAC0_AHB>, + <&syscrg JH7110_SYSCLK_GMAC0_PTP>, + <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "gtx"; + resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, + <&aoncrg JH7110_AONRST_GMAC0_AHB>; + reset-names = "stmmaceth", "ahb"; + interrupts = <7>, <6>, <5>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <256>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; + starfive,syscon = <&aon_syscon 0xc 0x12>; + status = "disabled"; + }; + + gmac1: ethernet@16040000 { + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg = <0x0 0x16040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, + <&syscrg JH7110_SYSCLK_GMAC1_AHB>, + <&syscrg JH7110_SYSCLK_GMAC1_PTP>, + <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, + <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "gtx"; + resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, + <&syscrg JH7110_SYSRST_GMAC1_AHB>; + reset-names = "stmmaceth", "ahb"; + interrupts = <78>, <77>, <76>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <256>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; + starfive,syscon = <&sys_syscon 0x90 0x2>; + status = "disabled"; + }; + + dma: dma-controller@16050000 { + compatible = "starfive,jh7110-axi-dma"; + reg = <0x0 0x16050000 0x0 0x10000>; + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>, + <&stgcrg JH7110_STGCLK_DMA1P_AHB>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>, + <&stgcrg JH7110_STGRST_DMA1P_AHB>; + interrupts = <73>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <3>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + }; + aoncrg: clock-controller@17000000 { compatible = "starfive,jh7110-aoncrg"; reg = <0x0 0x17000000 0x0 0x10000>; @@ -529,6 +987,12 @@ #reset-cells = <1>; }; + aon_syscon: syscon@17010000 { + compatible = "starfive,jh7110-aon-syscon", "syscon"; + reg = <0x0 0x17010000 0x0 0x1000>; + #power-domain-cells = <1>; + }; + aongpio: pinctrl@17020000 { compatible = "starfive,jh7110-aon-pinctrl"; reg = <0x0 0x17020000 0x0 0x10000>; @@ -546,5 +1010,40 @@ interrupts = <111>; #power-domain-cells = <1>; }; + + ispcrg: clock-controller@19810000 { + compatible = "starfive,jh7110-ispcrg"; + reg = <0x0 0x19810000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, + <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, + <&dvp_clk>; + clock-names = "isp_top_core", "isp_top_axi", + "noc_bus_isp_axi", "dvp_clk"; + resets = <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, + <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_ISP>; + }; + + voutcrg: clock-controller@295c0000 { + compatible = "starfive,jh7110-voutcrg"; + reg = <0x0 0x295c0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmitx0_pixelclk>; + clock-names = "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_VOUT>; + }; }; }; diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index 06257bfd9ac1..467ccab3bfaa 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -1,11 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk> + * Copyright 2022 StarFive Technology Co., Ltd. */ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +/* PLL clocks */ +#define JH7110_PLLCLK_PLL0_OUT 0 +#define JH7110_PLLCLK_PLL1_OUT 1 +#define JH7110_PLLCLK_PLL2_OUT 2 +#define JH7110_PLLCLK_END 3 + /* SYSCRG clocks */ #define JH7110_SYSCLK_CPU_ROOT 0 #define JH7110_SYSCLK_CPU_CORE 1 @@ -218,4 +225,77 @@ #define JH7110_AONCLK_END 14 +/* STGCRG clocks */ +#define JH7110_STGCLK_HIFI4_CLK_CORE 0 +#define JH7110_STGCLK_USB0_APB 1 +#define JH7110_STGCLK_USB0_UTMI_APB 2 +#define JH7110_STGCLK_USB0_AXI 3 +#define JH7110_STGCLK_USB0_LPM 4 +#define JH7110_STGCLK_USB0_STB 5 +#define JH7110_STGCLK_USB0_APP_125 6 +#define JH7110_STGCLK_USB0_REFCLK 7 +#define JH7110_STGCLK_PCIE0_AXI_MST0 8 +#define JH7110_STGCLK_PCIE0_APB 9 +#define JH7110_STGCLK_PCIE0_TL 10 +#define JH7110_STGCLK_PCIE1_AXI_MST0 11 +#define JH7110_STGCLK_PCIE1_APB 12 +#define JH7110_STGCLK_PCIE1_TL 13 +#define JH7110_STGCLK_PCIE_SLV_MAIN 14 +#define JH7110_STGCLK_SEC_AHB 15 +#define JH7110_STGCLK_SEC_MISC_AHB 16 +#define JH7110_STGCLK_GRP0_MAIN 17 +#define JH7110_STGCLK_GRP0_BUS 18 +#define JH7110_STGCLK_GRP0_STG 19 +#define JH7110_STGCLK_GRP1_MAIN 20 +#define JH7110_STGCLK_GRP1_BUS 21 +#define JH7110_STGCLK_GRP1_STG 22 +#define JH7110_STGCLK_GRP1_HIFI 23 +#define JH7110_STGCLK_E2_RTC 24 +#define JH7110_STGCLK_E2_CORE 25 +#define JH7110_STGCLK_E2_DBG 26 +#define JH7110_STGCLK_DMA1P_AXI 27 +#define JH7110_STGCLK_DMA1P_AHB 28 + +#define JH7110_STGCLK_END 29 + +/* ISPCRG clocks */ +#define JH7110_ISPCLK_DOM4_APB_FUNC 0 +#define JH7110_ISPCLK_MIPI_RX0_PXL 1 +#define JH7110_ISPCLK_DVP_INV 2 +#define JH7110_ISPCLK_M31DPHY_CFG_IN 3 +#define JH7110_ISPCLK_M31DPHY_REF_IN 4 +#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5 +#define JH7110_ISPCLK_VIN_APB 6 +#define JH7110_ISPCLK_VIN_SYS 7 +#define JH7110_ISPCLK_VIN_PIXEL_IF0 8 +#define JH7110_ISPCLK_VIN_PIXEL_IF1 9 +#define JH7110_ISPCLK_VIN_PIXEL_IF2 10 +#define JH7110_ISPCLK_VIN_PIXEL_IF3 11 +#define JH7110_ISPCLK_VIN_P_AXI_WR 12 +#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13 + +#define JH7110_ISPCLK_END 14 + +/* VOUTCRG clocks */ +#define JH7110_VOUTCLK_APB 0 +#define JH7110_VOUTCLK_DC8200_PIX 1 +#define JH7110_VOUTCLK_DSI_SYS 2 +#define JH7110_VOUTCLK_TX_ESC 3 +#define JH7110_VOUTCLK_DC8200_AXI 4 +#define JH7110_VOUTCLK_DC8200_CORE 5 +#define JH7110_VOUTCLK_DC8200_AHB 6 +#define JH7110_VOUTCLK_DC8200_PIX0 7 +#define JH7110_VOUTCLK_DC8200_PIX1 8 +#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9 +#define JH7110_VOUTCLK_DSITX_APB 10 +#define JH7110_VOUTCLK_DSITX_SYS 11 +#define JH7110_VOUTCLK_DSITX_DPI 12 +#define JH7110_VOUTCLK_DSITX_TXESC 13 +#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14 +#define JH7110_VOUTCLK_HDMI_TX_MCLK 15 +#define JH7110_VOUTCLK_HDMI_TX_BCLK 16 +#define JH7110_VOUTCLK_HDMI_TX_SYS 17 + +#define JH7110_VOUTCLK_END 18 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h index d78e38690ceb..eaf4a0d84f6a 100644 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> + * Copyright (C) 2022 StarFive Technology Co., Ltd. */ #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ @@ -151,4 +152,63 @@ #define JH7110_AONRST_END 8 +/* STGCRG resets */ +#define JH7110_STGRST_SYSCON 0 +#define JH7110_STGRST_HIFI4_CORE 1 +#define JH7110_STGRST_HIFI4_AXI 2 +#define JH7110_STGRST_SEC_AHB 3 +#define JH7110_STGRST_E24_CORE 4 +#define JH7110_STGRST_DMA1P_AXI 5 +#define JH7110_STGRST_DMA1P_AHB 6 +#define JH7110_STGRST_USB0_AXI 7 +#define JH7110_STGRST_USB0_APB 8 +#define JH7110_STGRST_USB0_UTMI_APB 9 +#define JH7110_STGRST_USB0_PWRUP 10 +#define JH7110_STGRST_PCIE0_AXI_MST0 11 +#define JH7110_STGRST_PCIE0_AXI_SLV0 12 +#define JH7110_STGRST_PCIE0_AXI_SLV 13 +#define JH7110_STGRST_PCIE0_BRG 14 +#define JH7110_STGRST_PCIE0_CORE 15 +#define JH7110_STGRST_PCIE0_APB 16 +#define JH7110_STGRST_PCIE1_AXI_MST0 17 +#define JH7110_STGRST_PCIE1_AXI_SLV0 18 +#define JH7110_STGRST_PCIE1_AXI_SLV 19 +#define JH7110_STGRST_PCIE1_BRG 20 +#define JH7110_STGRST_PCIE1_CORE 21 +#define JH7110_STGRST_PCIE1_APB 22 + +#define JH7110_STGRST_END 23 + +/* ISPCRG resets */ +#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0 +#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1 +#define JH7110_ISPRST_M31DPHY_HW 2 +#define JH7110_ISPRST_M31DPHY_B09_AON 3 +#define JH7110_ISPRST_VIN_APB 4 +#define JH7110_ISPRST_VIN_PIXEL_IF0 5 +#define JH7110_ISPRST_VIN_PIXEL_IF1 6 +#define JH7110_ISPRST_VIN_PIXEL_IF2 7 +#define JH7110_ISPRST_VIN_PIXEL_IF3 8 +#define JH7110_ISPRST_VIN_SYS 9 +#define JH7110_ISPRST_VIN_P_AXI_RD 10 +#define JH7110_ISPRST_VIN_P_AXI_WR 11 + +#define JH7110_ISPRST_END 12 + +/* VOUTCRG resets */ +#define JH7110_VOUTRST_DC8200_AXI 0 +#define JH7110_VOUTRST_DC8200_AHB 1 +#define JH7110_VOUTRST_DC8200_CORE 2 +#define JH7110_VOUTRST_DSITX_DPI 3 +#define JH7110_VOUTRST_DSITX_APB 4 +#define JH7110_VOUTRST_DSITX_RXESC 5 +#define JH7110_VOUTRST_DSITX_SYS 6 +#define JH7110_VOUTRST_DSITX_TXBYTEHS 7 +#define JH7110_VOUTRST_DSITX_TXESC 8 +#define JH7110_VOUTRST_HDMI_TX_HDMI 9 +#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10 +#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11 + +#define JH7110_VOUTRST_END 12 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ |